Building coreboot on well-supported platform such as Bay Trail is a quite straightforward task, however, we need to remember about some things in order to have coreboot working. First of all, we need to provide up-to-date microcode and FSP (Firmware Support Package), which are not included in coreboot source tree and coreboot build system won’t complain about it. Second thing is that Bay Trail has TXE firmware on the same ROM as boot firmware so we have to make sure that we won’t corrupt it because it would brick the platform. Except those we have a standard procedure, we need to get a toolchain.

Microcode Newest microcode can be found on

cloud.3mdeb.com We have to provide it because it’s a condition for warranty for CPU. It is provided as Intel-syntax assembly file with microcode as though it was ordinary data:

details of it’s structure are confidential. However for coreboot we need to provide it as comma separated list of values in C-style format, like this:

We can easly download and convert it using simple script:

FSP (Firmware Support Package) FSP is a binary package from Intel dedicated to firmware developers containing most important platform initialization (including IP). However, there is a non-FSP version of coreboot for Bay Trail, however, it won’t work without MRC (Memory Reference Code) which is confidential (available for trusted vendors) so we won’t cover this option. Intel sites redirect to

Github/IntelFsp/FSP (branch BayTrail) where you can find it. We are interested mostly in BayTrailFspBinPkg/FspBin/BayTrailFSP.fd which is file we have to provide to coreboot. FSP can be configured using BCT (Binary Configuration Tools), which is needed to enable Secure boot and FastBoot. The tool is available only as the Windows application but works well using Wine too. In the same package, you can find VgaBIOS which can be used too if you want to use a graphics card: BayTrailFspBinPkg/Vbios/Vga.dat

ME region Despite the name, ME region contains TXE firmware, as mentioned, we must not corrupt it. The simplest way to avoid that is to read ROM layout from original firmware image. In

utils/ifdtool of coreboot source tree we can find a program for reading layout from ROM image. The image can be taken from firmware package or read using flashrom, using SPI interface:

Note that you may need to adjust

-p option according to used SPI programmer. Use -p internal if you use MinnowBoard’s internal programmer.

While flashing coreboot we should inform flashrom only to write

bios region

Be careful because this layout may vary between versions, so we should check it for each version separately. For mass reproduction, it could be useful to read original firmware, apply coreboot on that image and flash it as a whole on each device. In case of using wrong layout resulting in bricked platform flash stock firmware (or backup), reread layout and flash coreboot again.

Toolchain coreboot needs specific versions of toolchain components, we have to take care of this. Makefile has a rule for building toolchain:

Despite the fact that that we usually want to boot 64-bit OS, coreboot code is compiled for 32-bit. Moreover, we have noticed that there’s a problem with libpayload on 64-bit toolchain. However, this procedure may be problematic. It may take much more time on an older machine and compilation may fail on some GCC versions. It’s much easier to use docker, there is dedicated docker image with toolchain for coreboot:

Docker intall guide There is also our image with additional FSP package (under default path): 3mdeb/coreboot-trainings-sdk:latest. To run shell in docker environment:

NOTE: remember that it works as root, so you may want to change the owner of new files after build. This command must be run in coreboot directory (there is

$PWD in mount parameter -v).

Configuration coreboot is configured using

make menuconfig similar to Linux Kernel (needs ncurses library). First, in Mainboard menu we set platform: Mainboard vendor (Intel) —> Mainboard model (Minnow Max) —> Except this we have to configure microcode and enable FSP in

Chipset menu: Include CPU microcode in CBFS (Include external microcode header files) —> (M0130673321.h M0130679901.h M023067221D.h) List of space-separated microcode header

Devices: [*] Add a VGA BIOS image (../intel/cpu/baytrail/vbios/Vga.dat) VGA BIOS path and filename (NEW) On x86 by default, coreboot chooses

SeaBIOS as a payload so that it provides legacy BIOS interface. You may want to use one of the other options: GRUB (well known, robust Open Source boot loader), Tianocore (UEFI), etc. This is a minimal configuration for MinnowBoard. However, you probably want to decrease log level (defualt 8:SPEW is much too verbose) in Console menu: Default console log level (5: NOTICE) —>

Build & Flash When the configuration is complete, we can save it and run:

flashrom so you have to do that outside container: sudo flashrom -l mb.layout -i bios -p dediprog -w build/coreboot.rom

Conclusion This procedure is pretty straightforward, but in practice turns out to cause much trouble at the first time. It also covers only most basic options. We are open to help if you have any problems with that. Also if you don’t want to do that we do provide such a service.